| Title | : | Secure Memory Disambiguation: Mitigating Performance-Induced Security Vulnerabilities |
| Speaker | : | Ms. Gayathri S (IIT Madras) |
| Details | : | Fri, 6 Feb, 2026 10:00 AM @ SSB 334 |
| Abstract: | : | Speculative execution is a cornerstone of performance optimization in modern out-of-order processors, yet it has introduced a broad class of microarchitectural side channels. This talk investigates performance-induced security vulnerabilities that arise from aggressive memory disambiguation mechanisms in speculative processors. While most prior defenses focus on speculative data leakage, recent work has shown that the memory ordering logic itself can leak fine-grained structural information through deterministic timing variations, enabling unprivileged adversaries to infer address mappings and amplify other microarchitectural attacks. A central challenge is that these vulnerabilities stem directly from performance-critical speculation mechanisms, creating an inherent challenge in balancing security and efficiency. Traditional mitigation approaches either disable speculation entirely or introduce prohibitive performance overheads, making them impractical for deployment. This thesis presents a lightweight hardware defense that mitigates these attacks by obfuscating deterministic patterns in speculative memory-dependency resolution while preserving the performance benefits of aggressive out-of-order execution. We validate the proposed approach through cycle-accurate microarchitectural simulation and hardware synthesis, demonstrating effective suppression of timing-based leakage with negligible performance degradation and minimal hardware cost. This work contributes both a practical defense mechanism and insights into design principles for reconciling performance-oriented speculation with security requirements in future processor architectures. |
