Research Publications -@ CSE-IITM

Publications by the members of CSE Department :

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Interconnect Aware Test Power Reduction.

, Nitin Chandrachoodan, V. Kamakoti
Appeared in J. Low Power Electronics, Vol 8, pp.516-525, 2012.

Towards Quick Solutions for Generalized Placement Problem.

S. Srinivasan 0001, V. Kamakoti, A. Bhattacharya
Appeared in International Symposium on Electronic System Design, ISED 2011, Kochi, Kerala, India, December 19-21, 2011 (ISED 2011), pp.106-111, Dec 2011.

Reconstructing Hardware Transactional Memory for Workload Optimized Systems.

Kunal Korgaonkar, Prabhat Jain, Deepak Tomar, Kashyap Garimella, V. Kamakoti
Appeared in Advanced Parallel Processing Technologies - 9th International Symposium, APPT 2011, Shanghai, China, September 26-27, 2011. Proceedings (APPT 2011), Lecture Notes in Computer Science, Vol 6965, pp.1-15, Sep 2011.

A Simulation Based Buffer Sizing Algorithm for Network on Chips.

Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli
Appeared in IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India (ISVLSI 2011), pp.206-211, Jul 2011.

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction.

, Nitin Chandrachoodan, V. Kamakoti
Appeared in IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India (ISVLSI 2011), pp.319-320, Jul 2011.

A Method for Integrating Network-on-Chip Topologies with 3D ICs.

M. Pawan Kumar, Anish S. Kumar, Srinivasan Murali, Luca Benini, V. Kamakoti
Appeared in IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India (ISVLSI 2011), pp.60-65, Jul 2011.

Hardware based genetic evolution of self-adaptive arbitrary response FIR filters.

Shoaib Mohammed, Sk. Noor Mahammad, V. Kamakoti
Appeared in Appl. Soft Comput., Vol 11, pp.842-854, 2011.

ROSY: recovering processor and memory systems from hard errors.

Karthik Raghavan, V. Kamakoti
Appeared in Operating Systems Review, Vol 45, pp.82-84, 2011.

Constructing Online Testable Circuits Using Reversible Logic.

Sk. Noor Mahammad, V. Kamakoti
Appeared in IEEE Trans. Instrumentation and Measurement, Vol 59, pp.101-109, 2010.

Impact of Temperature on Test Quality.

Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti
Appeared in VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp.276-281, Jan 2010.

Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation.

Kavish Seth, V. Kamakoti, S. Srinivasan
Appeared in TBC, Vol 56, pp.467-480, 2010.

Efficient Grouping of Fail Chips for Volume Yield Diagnostics.

Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi
Appeared in VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp.97-102, Jan 2009.

HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions.

K. Kunal, K. George, M. Gautam, V. Kamakoti
Appeared in Operating Systems Review, Vol 43, pp.98-99, 2009.

Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures.

George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi
Appeared in J. Low Power Electronics, Vol 5, pp.58-68, 2009.

Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits.

K. Shyamala, J. Vimalkumar, V. Kamakoti
Appeared in J. Low Power Electronics, Vol 5, pp.429-438, 2009.

Automatic Constraint Based Test Generation for Behavioral HDL Models.

Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil
Appeared in IEEE Trans. VLSI Syst., Vol 16, pp.408-421, 2008.

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction.

V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
Appeared in J. Low Power Electronics, Vol 4, pp.101-110, 2008.

LFSR Based Stream Ciphers Are Vulnerable to Power Attacks.

Sanjay Burman, Debdeep Mukhopadhyay, V. Kamakoti
Appeared in Progress in Cryptology - INDOCRYPT 2007, 8th International Conference on Cryptology in India, Chennai, India, December 9-13, 2007, Proceedings (INDOCRYPT 2007), Lecture Notes in Computer Science, Vol 4859, pp.384-392, Dec 2007.

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Appeared in 2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007 (ITC 2007), pp.1-10, Oct 2007.

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test.

V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
Appeared in 2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007 (ITC 2007), pp.1-9, Oct 2007.

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Appeared in 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA (VTS 2007), pp.167-172, May 2007.

Power Virus Generation Using Behavioral Models of Circuits.

K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula
Appeared in 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA (VTS 2007), pp.35-42, May 2007.

Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Appeared in 2007 Design, Automation and Test in Europe Conference and Exposition (DATE 2007), April 16-20, 2007, Nice, France (DATE 2007), pp.534-539, Apr 2007.

Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Appeared in 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India (ICES 2007), pp.351-356, Jan 2007.

Controllability-driven Power Virus Generation for Digital Circuits.

K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
Appeared in 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India (ICES 2007), pp.407-412, Jan 2007.

A novel approach to the placement and routing problems for field programmable gate arrays.

Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti
Appeared in Appl. Soft Comput., Vol 7, pp.455-470, 2007.

Variation-Tolerant, Power-Safe Pattern Generation.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Appeared in IEEE Design & Test of Computers, Vol 24, pp.374-384, 2007.

Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits.

K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
Appeared in J. Low Power Electronics, Vol 3, pp.280-292, 2007.

System-on-programmable-chip implementation for on-line face recognition.

A. Pavan Kumar, V. Kamakoti, Sukhendu Das
Appeared in Pattern Recognition Letters, Vol 28, pp.342-349, 2007.

Delay and peak power minimization for on-chip buses using temporal redundancy.

K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
Appeared in Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 (VLSI 2006), pp.119-122, Apr 2006.

An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.

Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti
Appeared in 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp.507-510, Jan 2006.

Ultra Folded High-Speed Architectures for Reed-Solomon Decoders.

Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti
Appeared in 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp.517-520, Jan 2006.

On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Appeared in J. Low Power Electronics, Vol 2, pp.464-476, 2006.

Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses.

K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
Appeared in J. Low Power Electronics, Vol 2, pp.425-436, 2006.

A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores.

K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil
Appeared in 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India (ATS 2005), pp.40-45, Dec 2005.

Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.

E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan
Appeared in 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA (IPDPS 2005), Apr 2005.

FPGA based Agile Algorithm-On-Demand Co-Processor.

Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti
Appeared in 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany (DATE 2005), pp.82-83, Mar 2005.

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only).

E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan
Appeared in Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005 (FPGA 2005), pp.265, Feb 2005.

A function generator-based reconfigurable system.

Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti
Appeared in Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp.905-909, Jan 2005.

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.

E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan
Appeared in Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp.1200-1203, Jan 2005.

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.

Vivek Garg, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti
Appeared in Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp.791-794, Jan 2005.

A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip.

K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti
Appeared in 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp.207-212, Jan 2005.

A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation.

Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti
Appeared in 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp.795-798, Jan 2005.

Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.

E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Narayanan Vijaykrishnan
Appeared in 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp.736-741, Jan 2005.

Pseudo-online testing methodologies for various components of field programmable gate arrays.

L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti
Appeared in Microprocessors and Microsystems, Vol 29, pp.99-119, 2005.

Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines.

R. Manimegalai, E. Siva Soumya, V. Muralidharan, Balaraman Ravindran, V. Kamakoti, D. Bhatia
Appeared in 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp.451-456, Jan 2005.

SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis.

R. Manimegalai, B. Jayaram, A. Manoj Kumar, V. Kamakoti
Appeared in Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004, pp.57-64, Dec 2004.

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.

E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashiknth, V. Kamakoti, Vijaykrishnan Narayanan
Appeared in Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004, pp.121-128, Dec 2004.

An Architecture for Real Time Face Recognition Using WMPCA.

A. Pavan Kumar, V. Kamakoti, Sukhendu Das
Appeared in ICVGIP 2004, Proceedings of the Fourth Indian Conference on Computer Vision, Graphics & Image Processing, Kolkata, India, December 16-18, 2004 (ICVGIP 2004), pp.644-649, Dec 2004.

A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN.

Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti
Appeared in Neural Information Processing, 11th International Conference, ICONIP 2004, Calcutta, India, November 22-25, 2004, Proceedings (ICONIP 2004), Lecture Notes in Computer Science, Vol 3316, pp.327-332, Nov 2004.

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